Hardware Description Languages

Abstract

Until the mid-1980s most digital chips were designed as drawings: schematics of gates, then hand-cut layouts. Hardware description languages (HDLs) let engineers write a circuit as text, simulate it, and from the late 1980s have software synthesise the gates automatically. Two languages won. Verilog was written by Phil Moorby at the start-up Gateway Design Automation over Christmas 1983 and sold from 1985; VHDL came out of a US Defense Department contract of 1983 and borrowed its syntax from Ada. Synopsys built logic synthesis on Verilog from 1987, Cadence bought Gateway and opened the language in 1990, and both became IEEE standards. By 2018 about 80 per cent of chip design teams used Verilog or its successor SystemVerilog.

From Drawings to Text

Through the 1970s a chip was drawn: logic designers produced schematics, and layout designers cut the geometry of each layer out of red rubylith film, which was photographically reduced to make the masks (see Semiconductor Fabrication). Carver Mead and Lynn Conway’s Introduction to VLSI Systems (1980) simplified layout rules so that computer scientists could design chips, but the design itself was still a picture (see Lynn Conway and VLSI and The Integrated Circuit Revolution).

Textual descriptions of hardware existed in research. In their 1971 book Computer Structures, C. Gordon Bell and Allen Newell described computers at the register-transfer level, the level of registers and the operations that move data between them, and used a notation called ISP to describe DEC’s PDP-8. Other languages followed for teaching and research, such as AHPL and, around 1979, KARL at the University of Kaiserslautern; in 1983 Data I/O introduced ABEL for programming logic devices. In industry, simulators read netlists, lists of gates and their connections. One of them was HILO, developed in Britain, first at Brunel University; Phil Moorby, a mathematics graduate of Southampton with a master’s in computer science from Manchester, joined its team full time in 1979 and wrote the simulators for HILO-2 and HILO-3. One of HILO’s few early customers was Prabhu Goel, who bought it for Wang Laboratories in Massachusetts and, in Moorby’s words, “found lots of bugs for us too”.

Verilog

Goel left Wang to found a company of his own, Automated Integrated Design Systems, later renamed Gateway Design Automation, and recruited Moorby. Over Christmas 1983, staying at Goel’s house, Moorby and Chi-Lai Huang worked out a new language that could describe both gate-level netlists and behaviour in a procedural style. Its gate-level syntax followed HILO’s. Moorby developed the compiler and simulator on a Sun-2 workstation while the rest of Gateway was programming in Fortran on an IBM mainframe. In the first quarter of 1985 the product needed a name for Sun’s catalogue; Moorby combined “verification” and “logic” into Verilog. The first copy went to Apollo, which, to Moorby’s relief, put it on the shelf; another customer took about six months more to start using it.

Gateway’s simulator, later Verilog-XL, was fast. Benchmarks for AMD put the software simulator within a factor of two or three of Zycad’s hardware accelerators, which sold for about a million dollars. Verilog-XL became the standard sign-off simulator for ASICs, the final check a design passed before a foundry would build it.

VHDL

The US Department of Defense had a different problem. Its contractors were putting custom chips into weapons systems, and it wanted their behaviour documented in a form that would outlast the contractors. Its Very High Speed Integrated Circuits (VHSIC) programme gave rise to the VHSIC Hardware Description Language, developed under an Air Force contract awarded in 1983 to Intermetrics as prime contractor, with Texas Instruments and IBM. The Defense Department required its syntax to follow Ada as closely as possible (see Ada: The Language the Pentagon Built), which made VHDL strongly typed and verbose. It became IEEE Standard 1076 in 1987, and military procurement rules (MIL-STD-454) required ASIC documentation in VHDL. It was an open standard from the start.

Synthesis

What turned HDLs from documentation into the design itself was logic synthesis: software that reads a register-transfer-level description and produces an optimised gate netlist for a given chip technology. Synopsys, founded in 1986 in North Carolina’s Research Triangle Park as Optimal Solutions by Aart de Geus and colleagues from General Electric’s computer-aided engineering group, and renamed and moved to Mountain View in 1987, sold the first widely used synthesis tool, Design Compiler. Of the three synthesis companies of the time, Moorby recalled, Synopsys was the one that “jumped onto Verilog”, and Gateway worked with it to settle details such as how bit widths extend in expressions, so that simulation and synthesis gave the same result. Designers could now write a few thousand lines of Verilog instead of drawing tens of thousands of gates.

Standards

Cadence Design Systems bought Gateway, in 1989 by the Computer History Museum’s dating and 1990 by others. Verilog was still proprietary, and customers, watching the open VHDL gain support, pressed Cadence to open it. In 1990 Cadence handed the language to a new body, Open Verilog International. Moorby later doubted that the exact timing mattered: “if it opened up like two years before it did, or two years after, I’m not sure whether it would have made any difference.” Verilog became IEEE Standard 1364 in 1995, with revisions in 2001 and 2005. SystemVerilog, on which Moorby worked at Co-Design Automation and, from 2002, at Synopsys, added verification features and was standardised as IEEE 1800 in 2005; in 2009 the two standards were merged.

Newer languages raise the level further: SystemC describes hardware in C++, and Chisel, from Berkeley, embeds hardware construction in the Scala programming language. Moorby received the Phil Kaufman Award for Verilog in 2005 and was made a Fellow of the Computer History Museum in 2016. He died on 15 September 2022.