Dead End: ILLIAC IV

Abstract

ILLIAC IV was meant to be the first computer to perform a billion floating-point operations per second, by running one instruction on 256 processors at once. Designed by Daniel Slotnick at the University of Illinois under an ARPA contract signed in 1964 and built by Burroughs, it shrank to a quarter of its plan, rose in cost from $8 million to $31 million, was driven off campus by anti-war protests, and reached NASA’s Ames Research Center in 1972 in a state that took three more years to make usable. It then did valuable fluid-dynamics work until 1981. Its programming model, a single instruction stream over an array of processors, lost to vector machines like the Cray-1 and returned only in specialised forms.

The single ILLIAC IV quadrant at NASA Ames, 1972, with a processing unit pulled out. Image: NASA Ames Research Center / Lee Jones, public domain, via Wikimedia Commons.

Slotnick’s Array

Daniel Slotnick (1931–1985) worked as a young man on the IAS computer at Princeton, where in 1952 he came up with the idea of many simple processors obeying one control unit. John von Neumann was not persuaded (see John von Neumann). In 1958 Slotnick and John Cocke published the idea, and from 1960 Slotnick designed SOLOMON at Westinghouse under an Air Force contract: a grid of processing elements, each with its own memory, all executing the same instruction on different data. When the Air Force money ran out in 1964, he took the design to the University of Illinois, whose ILLIAC series of computers went back to 1952, and the university signed a contract with ARPA for an enlarged version.

The plan was 256 processing elements (PEs), each a 64-bit floating-point processor with 2,048 words of its own memory, arranged in four quadrants of 64, each quadrant under one control unit. At a 25 MHz clock the machine was to deliver a billion floating-point operations per second, at an estimated cost of $8 million. Today the scheme is called SIMD, single instruction, multiple data (see Concurrency and Parallelism).

Building It

Burroughs won the construction contract in 1966, with Texas Instruments to supply integrated circuits in 64-pin packages. TI could not make them work: crosstalk forced a redesign to 16-pin packages, which spread the logic over more boards and cut the clock from 25 to 16 MHz. That change alone cost about two years and millions of dollars. In 1969, with the money running out, ARPA and the university agreed to build one quadrant of 64 PEs instead of four.

The processing-element memory was a second gamble. Instead of magnetic core, the project bought semiconductor memory from Fairchild, built from its new 256-bit bipolar chips, 131,072 bits per PE. The Computer History Museum calls it the first commercial use of commodity semiconductor memory in a large computer; it was controversial at the time and is one of the parts of the project that aged well (see Robert Noyce and Fairchild Semiconductor).

The Protests

The machine was to stand on the Urbana campus, and its money came from the Defense Department. On 6 January 1970 the Daily Illini reported that it would be used to design nuclear weapons. After the Kent State shootings in May 1970, Illinois students joined the national student strike with a “day of Illiaction” on 9 May; in August a bomb at the Army Mathematics Research Center in the University of Wisconsin’s Sterling Hall killed a researcher. In January 1971 the decision was taken to install the computer at NASA’s Ames Research Center in California instead.

Ames

ILLIAC IV was delivered to Ames in April 1972 and installed in building N-233, a single quadrant 15 metres long and 3 metres high. The final cost was $31 million. Dates in secondary sources vary: the Computer History Museum has it delivered in 1971 in one timeline entry and “does not operate until 1972” in another. Neither means it worked. The first programs ran in the summer of 1973 with doubtful results. Between June and September 1975 engineers spent four months repairing it, replaced 110,000 resistors and lowered the clock to 13 MHz. It was counted operational from late 1975, was connected to the ARPANET in November 1975, and ran its first successful applications in 1976.

Even then, Ames scheduled it from Monday morning to Friday afternoon, 60 hours of uptime against 44 hours of planned maintenance each week. “It was good for up to a week,” Eugene Miya of Ames recalled of its hardware. Peak speed was about 50 MFLOPS, a twentieth of the goal; early codes managed around 15. For the problems it suited, though, it was fast. Ames’s computational fluid dynamics group wrote in its own languages, CFD and Vectoral, and on aerodynamic flow calculations the machine beat the CDC 7600 by two to six times. ILLIAC IV was switched off on 7 September 1981 and decommissioned in 1982.

Why It Failed

Dead End

ILLIAC IV failed as a project before it failed as an architecture. It was late by years and over budget by a factor of four, and the custom circuits, the new memory and a new machine organisation all had to work at once. By the time the one quadrant ran properly, Seymour Cray’s vector design had reached the market: the Cray-1 of 1976 was a single processor with vector registers, ran ordinary Fortran with a vectorising compiler, and was reliable (see Seymour Cray and Supercomputing).

The SIMD array asked programmers to lay out their data across a fixed grid of processors and to keep all of them busy. Problems that fit, such as finite-difference grids in fluid dynamics, ran well; most others did not. Ames’s own users, by Miya’s account, ignored the ALGOL-like Glypnir and the parallel Fortran dialects and wrote in languages made for their equations.

The idea itself returned more than once. Danny Hillis’s Connection Machine of 1986 put 65,536 one-bit processors under one instruction stream before his company moved to independent processors with the CM-5 (see Danny Hillis and the Connection Machine). Since then single-instruction, multiple-data execution has moved inside the chip, into the vector units of ordinary processors and the thread groups of GPUs (see The Supercomputer Era).