Dead End: Intel NetBurst

Abstract

NetBurst was the microarchitecture of Intel’s Pentium 4, built on the premise that clock frequency would keep climbing. Intel doubled the pipeline to 20 stages so each stage did less work and the clock could run faster, and said the design would scale to 10 GHz. It launched in November 2000 at 1.5 GHz, slower in many programs than the 1 GHz Pentium III it replaced. Four years later the 90-nanometre Prescott version, with a 31-stage pipeline, hit a ceiling of 3.8 GHz and a heat problem that Intel could not engineer away. In 2004 Intel cancelled the 4 GHz Pentium 4 and the next two NetBurst designs. Its next generation came from a team in Haifa, Israel, whose low-power laptop chip descended from the older Pentium III.

A 1.5 GHz Pentium 4 “Willamette” for Socket 423, the first NetBurst processor (2000). Image: Futase_tdkr., public domain, via Wikimedia Commons.

The Frequency Bet

By the late 1990s Intel’s desktop processors all descended from the P6 microarchitecture of the 1995 Pentium Pro, carried forward in the Pentium II and Pentium III. The chief architect of that line, Bob Colwell, also worked on its successor before he left Intel in 2000. The successor was to be a clean start, and its central decision concerned the pipeline.

A processor pipeline works like an assembly line: each instruction passes through a series of stages (fetch, decode, schedule, execute, write back), and each stage hands its work to the next on every clock tick. The clock can tick only as fast as the slowest stage finishes its work. Cut the work into more, smaller stages and the clock can run faster. The cost appears when the processor guesses wrong about a branch, for example which way an if will go: every instruction already in the pipeline behind the wrong guess must be thrown away, and the deeper the pipeline, the more work is lost.

Intel chose depth. When it presented the new design at the Intel Developer Forum in San Jose on 22 August 2000, it named it NetBurst and called the deep pipeline “Hyper Pipelined Technology”: 20 stages, twice the P6. Albert Yu, head of the Intel Architecture Group, explained that it was the first new desktop processor microarchitecture for Intel since the P6, and the press release said Intel had set out to deliver “performance and frequency scalability well into the future.” The arithmetic units ran at twice the core clock (the “Rapid Execution Engine”); a new Execution Trace Cache stored about 12,000 already-decoded micro-operations so the decoder did not have to translate the same x86 instructions repeatedly; a 400 MHz system bus tripled the Pentium III’s bandwidth; and 144 new SSE2 instructions handled 128-bit integer and double-precision vector arithmetic. Seven of the designers described the machine in the Intel Technology Journal in the first quarter of 2001.

The other half of the bet was commercial. Clock speed was the one number on a PC advertisement that every buyer could compare, and a design whose main virtue was a higher clock could be sold with a single figure. Intel told the press that NetBurst could scale to 10 GHz.

Willamette

The first Pentium 4, code-named Willamette, went on sale on 20 November 2000 at 1.4 and 1.5 GHz. It had 42 million transistors on a 180-nanometre process and fitted a new socket, Socket 423. Its only chipset, the i850, required Rambus RDRAM, which cost far more than ordinary SDRAM.

Reviewers were unimpressed. PC World found that the 1.5 GHz Pentium 4 barely kept pace with the 1 GHz Pentium III machines it tested, fell behind them on some measures, and did worse against a 1.2 GHz AMD Athlon with DDR memory. Intel’s answer was that the chip was not designed to speed up standard office applications. It did well where its design paid off: streaming multimedia code recompiled for SSE2, and floating-point work with long, predictable loops. Ordinary branchy integer code, which was most of what a PC ran, paid the full penalty of the long pipeline.

Intel kept raising the clock. A 1.7 GHz model in April 2001 was the first that clearly beat the Pentium III, and in August 2001 the 2 GHz Pentium 4 arrived together with the 845 chipset, which finally allowed cheaper PC133 SDRAM. The chip was a sales success because the number on the box was larger than anyone else’s.

Gelsinger’s Warning

In February 2001, three months after the launch, Intel’s chief technology officer Pat Gelsinger gave the plenary talk at the International Solid-State Circuits Conference and described where the trend led. If chip design continued as it was going, he said, a processor would become a heat generator with the intensity of a nuclear reactor, and its power density would approach that of a rocket nozzle. His example was a 425-million-transistor die clocked at 30 GHz, which would dissipate 3,000 to 5,000 watts. “Going forward, I don’t think we know how to cool a 5000-watt processor,” he told the audience, and he named the alternatives: multithreading, which ran several tasks on one processor for 5 to 10 percent more logic, and aggressive switching-off of unused transistors. A “wider, deeper machine,” he said, would not deliver the power efficiency needed.

The physics behind the warning was simple. The dynamic power of a chip rises with its switching frequency and with the square of its supply voltage. For three decades each process shrink had allowed lower voltages, which offset the higher clock. By about 2000 the voltage could not drop much further without transistors leaking current when they were supposed to be off, and leakage got worse with every shrink. A design that bought its performance with frequency was buying it with heat.

Northwood and Hyper-Threading

The second Pentium 4, Northwood, moved to 130 nanometres in January 2002 and doubled the second-level cache to 512 KB. It was a better chip at the same pipeline depth, and it reached 3.06 GHz in November 2002. That model introduced Hyper-Threading, Intel’s version of simultaneous multithreading: the processor presented itself to the operating system as two logical processors and fed instructions from both threads into one set of execution units. On a deep pipeline that often sat idle waiting for memory or recovering from a mispredicted branch, a second thread filled some of the gaps. It was the first of Gelsinger’s remedies to ship.

In April 2003 the bus went to 800 MHz, in June 2003 the clock reached 3.2 GHz, and in September 2003 Intel announced a Pentium 4 Extreme Edition at $1,000, a Xeon-derived part with a large cache. Reviewers nicknamed it the “Emergency Edition”; AMD shipped its 64-bit Athlon 64 the same month.

The Megahertz Argument

AMD could not win a clock-speed contest against NetBurst and stopped trying to. Its Athlon did more work per clock cycle, and in October 2001 it launched the Athlon XP with model numbers in place of clock speeds: a chip labelled 1800+ ran well below 1.8 GHz and was meant to perform like one that did. AMD’s marketing manager Mark Bode told eWeek that megahertz had “been distorted as a proxy for performance.” The rating was officially measured against AMD’s own older Athlon, and everyone read it as a comparison with the Pentium 4. Analysts agreed that clock speed was a poor measure and doubted that buyers would follow the argument.

Intel came around three years later. With the Prescott generation in 2004 it introduced processor numbers of its own: three digits, a 5 for the Pentium 4 family, a 7 for the Pentium M, a 3 for the Celeron, with the remaining digits ranking a chip within its family by clock, cache and bus speed together. The company that had sold the gigahertz stopped printing it in the product name. (AMD’s own story is in AMD and the x86 Underdog.)

Prescott

Die of a Prescott Pentium 4 with 1 MB of cache, 90 nm. Image: Martijn Boer, public domain, via Wikimedia Commons.

Prescott launched on 2 February 2004, late, on Intel’s new 90-nanometre process. It had 125 million transistors, a 1 MB cache, and a pipeline lengthened again, from 20 to 31 stages. The four models on sale that day ran from 2.8 to 3.2 GHz, priced from $163 to $278; the 3.4 GHz Prescott followed in March. The deeper pipeline was meant to carry the chip to 4 GHz and beyond.

At equal clock speed Prescott was a little slower than the Northwood it replaced, because the longer pipeline lost more work on every wrong branch guess; reviewers noted that its improved branch prediction and prefetching recovered some but not all of the loss. The rest was supposed to come from frequency. Instead the 90-nanometre transistors leaked, and Prescott ran hot: the 3.2 GHz model was rated for a maximum of about 103 watts, and the fastest single-core desktop Pentium 4 was rated at 115 watts. On hardware forums the chip became “PresHot.” It never got past 3.8 GHz, reached in November 2004 with the Pentium 4 570.

The Cancellations

Prescott’s successor, Tejas, and its server counterpart Jayhawk were planned for 2005 with pipelines of 40 to 50 stages. On 7 May 2004 Intel cancelled both. “We are accelerating our dual-core schedule for 2005,” a spokesman told The Register; dual-core desktop chips would arrive 12 to 18 months earlier than planned.

On 14 October 2004 Intel dropped the 4 GHz Pentium 4. The chip had been due at the end of 2004 and had already slipped into 2005; now there would be a 3.8 GHz model with a cache growing from 1 MB to 2 MB, more emphasis on Hyper-Threading, and dual-core designs. Intel informed customers quietly and issued no press release. Its spokesman Bill Kircos told The Register that “it wasn’t a light switch that went on or off today,” then asked himself whether the change was an exclamation point and answered “Yes.” Another spokesman, George Alfs, conceded to eWeek that it was “a symbolically tough decision because of the magic ‘four’ number.”

The dual-core chips arrived in May 2005 as the Pentium D. The first, Smithfield, was two Prescott cores on one die, and it inherited Prescott’s power budget twice over.

Haifa

A 1.4 GHz Pentium M “Banias” (2003), the Haifa design derived from the Pentium III. Image: D-Kuru, CC BY-SA 3.0 AT, via Wikimedia Commons.

The replacement had been growing in parallel since 2000, in Intel’s Israel Development Center in Haifa. The Haifa team had designed the memory controller for Timna, a cancelled low-cost integrated processor that reused P6 parts, and so knew the P6 core in detail. Intel then gave the team a crash project: a backup processor for laptops. Its leader, Mooly Eden, later told InfoWorld, “We knew we’d hit a power wall before 2000, and we were aggressive in selling it to management.” Eden presented the plan to Intel’s executives in California in 2000, Paul Otellini (then president and chief operating officer) backed it, and the project was approved.

The design, code-named Banias after an ancient site in the Golan Heights, did not use NetBurst. It took the Pentium III core and rebuilt it for efficiency: a better decoder and front end, improved branch prediction, SSE2, a 1 MB cache, and a bus compatible with the Pentium 4’s. Intel launched it on 12 March 2003 as the Pentium M, the processor of its Centrino laptop platform, at 900 MHz to 1.7 GHz. A 1.6 GHz Pentium M matched or beat a 2.4 GHz mobile Pentium 4 while drawing far less power, and the mobile Pentium 4 was replaced. For Intel’s marketing it meant selling a chip with a lower clock as the better one; Eden recalled that the company had spent years teaching customers that faster clocks meant more performance. The Pentium M was not a retreat organised after NetBurst failed. It was a second line that Intel had kept alive for laptops, and when the desktop line ran out of road, it was the one available.

Its 90-nanometre successor, Dothan, launched in May 2004, the same month Tejas was cancelled. In January 2006 the dual-core Yonah, built on the “Enhanced Pentium M” design, appeared as the Core Duo.

Apple and Core

On 6 June 2005 Steve Jobs announced at Apple’s developer conference that the Macintosh would move from PowerPC to Intel processors. His argument was power: PowerPC chips, he said, offered 15 units of performance per watt on the roadmaps beyond 2006, Intel’s 70, and Apple could not get a G5 cool enough for a laptop. On stage he ran Mac OS X 10.4.1 on a 3.6 GHz Pentium 4, a NetBurst chip. The developers’ transition kits used it too. But the first Intel Macs, the iMac and MacBook Pro announced on 10 January 2006, used the Core Duo from Haifa, and no shipping Mac ever used a NetBurst processor. (The switch is told in The macOS Lineage.)

The Core microarchitecture, a refreshed successor to the Enhanced Pentium M and based in part on Intel Israel’s design, launched in the Xeon “Woodcrest” on 26 June 2006 and as the Core 2 Duo on 27 July 2006. Its pipeline had 14 stages, less than half of Prescott’s. Intel claimed 40 percent more performance than the Pentium D at 40 percent less power, and the desktop Conroe was rated at 65 watts. The P6 line that NetBurst had been meant to retire in 2000 was Intel’s main architecture again.

Intel released the last Pentium 4 revision, the 65-nanometre Cedar Mill, on 5 January 2006. It stopped taking orders for NetBurst processors on 7 December 2007 and made the final shipments on 8 August 2008. Hyper-Threading, absent from Core, came back with its successor Nehalem. The trace cache came back too: the later Sandy Bridge generation introduced a cache for decoded micro-operations built on the same idea.

Dead End

NetBurst failed because its premise expired while it was in production. The design traded work per clock for clock speed on the assumption that clock speed would keep rising at the historical rate. That assumption held through the 130-nanometre Northwood. At 90 nanometres, supply voltages stopped falling, leakage rose, and the frequency that a 31-stage pipeline needed to pay for itself could not be cooled at a price anyone would pay for a desktop PC. Gelsinger had described the problem in public three months after the first Pentium 4 shipped.

The marketing reasons for the bet made it hard to abandon. A single number was easy to sell, and as long as the number rose every quarter the Pentium 4 outsold faster-per-clock competitors. When the number stopped rising, Intel had no product story ready for the desktop, and it took two years and a team in Haifa to supply one. The industry’s answer to the power wall was the one Gelsinger had sketched in 2001: several cores and several threads per chip, at clock speeds that have changed little since, which made parallel software everyone’s problem (see Concurrency and Parallelism).

NetBurst is the third Intel architecture in this series that was meant to replace its predecessor and was outlived by it, after the iAPX 432 and the Itanium. All three times, the line Intel had meant to leave behind remained its mainstream product.